1. Technical Field
This invention relates to an electrically conductive interconnect in a semiconductor structure and, more particularly, to a liner positioned between the dielectric layer and the conductive interconnect for permitting a localized interconnect.
2. Description of the Related Art
With ongoing development of semiconductor device fabrication technology, the critical dimensions of interconnects are designed to provide signal paths that are electrically, mechanically, and cost efficiently robust. The interconnect lines are electrically isolated from other parts of the device. In conventional technology, a 130 nm process, for example, copper damascene, is one process used to form semiconductor device interconnects.
In the copper damascene and other device manufacturing processes, several techniques are used to form and shape structures of different material compositions. Such techniques include, but are not limited to, photolithography, anisotropic chemical or ion etching, chemical-mechanical planarization (CMP), plasma enhanced chemical vapor deposition (PECVD), and electroplating.
Copper damascene, however, has limitations not found in other techniques for forming conductive interconnects. For example, a damascene process is generally limited to very thin interconnects, e.g., 2-5 microns. For both thin and thicker interconnects however, e.g., across the range of 2-50 microns or more in height, other types of interconnect procedures are also available. Often, thick interconnects are about 7-10 microns.
In many applications, e.g., power applications, there is a need to pass high power signals. In such applications, the performance characteristics for interconnects are different from the performance characteristics of conventional memory or microprocessor signaling applications. In these power applications and other like applications, conductive films are formed with different dimensions. For example, if a copper interconnect design calls out a 5 or more microns interconnect height, the copper damascene process is no longer suitable.
As an alternative to copper damascene, another technique is available. This other technique is called a localized thick interconnect, and generally includes traditional photolithography and electroplating processes. The localized thick interconnect process can generate thick copper or other conductive interconnections from 2 to 50 microns or more in thickness. Traditional localized thick interconnect processes can produce unreliable interconnects.
FIGS. 1A-1E illustrate cross-sectional views of a progression of steps in a prior art conventional localized thick copper process for producing a copper line acting as a localized conductive interconnect. Interconnects are common structures in semiconductor based electronic devices. Several methods are available to produce an interconnect, and some examples known in the art will now be described.
FIG. 1A illustrates a semiconductor substrate wafer having various electronic components and foundational interconnect layers formed thereon. The substrate can be silicon monocrystalline silicon, or any other semiconductor suitable for forming electronic components.
In the embodiment of FIG. 1A, a dielectric layer 12 is formed on a monocrystalline silicon substrate 10 containing various electronic components. The dielectric layer 12 could be a combination of layers or a single layer. In some cases, a plasma enhanced chemical vapor deposition (PECVD) process deposits silicon nitride (Si3N4) or silicon oxynitride (SiON) or combinations thereof. A barrier material 14, also referred to as a barrier liner, is formed on the dielectric layer 12. The barrier material 14 is generally 0.2 to 0.5 microns thick, but could have other dimensions.
Preferably, the barrier material 14 will have sufficient resistance to the diffusive properties of the copper to prevent spoilage of the underlying electronic circuits and surrounding structures. The barrier material 14 should also preferably adhere well to the dielectric layer 12. In addition, the barrier material 14 will preferably be conductive and electrically bondable to the copper that will form the interconnect.
The barrier material 14, in cooperation with the dielectric layer 12, is useful to prevent copper atoms from a copper interconnect from diffusing to the surrounding structure and the silicon substrate 10. Without a proper barrier against copper diffusion, the underlying electronic components formed on the substrate 10 could be contaminated by the copper atoms from the interconnect.
In FIG. 1A, after the liner 14 is formed, a seed layer 16 of interconnect material, copper in this case, is deposited in some processes of the prior art. The seed layer 16 is generally 0.2 to 0.5 microns thick, but could have other dimensions. The seed layer 16, also called a plating base, is used to cover the wafer where electrical contact will be made with underlying circuitry. Accordingly, the seed layer 16 in this embodiment functions as an adhesion layer for the subsequently plated copper or copper base alloy that will form the interconnect.
Alternatively, an integrated physical vapor deposition (PVD) process could also be a method selected to deposit the seed layer 16. In addition, the PVD process may be used to deposit both the barrier liner 14 and the copper seed layer 16 together. Depositing both the barrier layer 14 and the seed layer 16 is helpful to reduce the possibility of delamination between these layers.
FIG. 1B illustrates a cross section of the structure of FIG. 1A after the deposition of the interconnect material 20. Prior to the deposition of the interconnect material 20, photoresist masking structures 18 are formed via standard lithography processes. The thickness of the photoresist can range from one micron to sixty microns or more depending on the interconnect thickness called out by the application.
After the photoresist mask 18 is formed, the interconnect material 20, copper in this example, is deposited. In the embodiment of FIG. 1B, the interconnect material 20 is deposited with an electroplating process, but other techniques can be used.
FIG. 1C illustrates the structure of FIG. 1B after further processing. In FIG. 1C, the photoresist mask 18 has been removed with a solvent strip treatment, which is used to preserve the integrity of the copper interconnect line. The interconnect structure 24 shows a seamless bond between what was the seed layer 16 and the interconnect material 20.
FIG. 1D illustrates a cross section of the intended interconnect 24 achieved with a localized thick interconnect process after additional etch steps. An etch step has removed the copper seed layer 16 as well as a little bit of the copper on the thick interconnect line 24. Another etch step has removed the exposed barrier liner 14 by using the copper interconnect line 24 as hard mask. The barrier etch chemistry is particularly selective so as to prevent removal of any further copper from the interconnect line 24. The remaining barrier material 22 is underlying the thick interconnect line 24.
The copper interconnect line 24 width results from the width of the photoresist mask 18 opening minus the copper material lost during the copper seed layer etch step. Similarly, the copper interconnect line 24 height results from the depth of the photoresist mask 18 opening, the amount of copper material 20 deposited in the photoresist mask 18 opening, and the amount of copper material sacrificed during the copper seed layer 16 etch step. In the embodiment of FIG. 1D, the final interconnect structure 24 is 5 to 15 microns high and at least 5 microns wide. In other embodiments, the final interconnect structure 24 can be 50 microns or more high and 50 microns or more wide or any other suitable dimensions.
In FIG. 1D, the structure shows a single interconnect line 24. Many interconnect lines can be formed at the same time. During the seed layer and copper deposition processes, the partially formed interconnects will be electrically shorted together. Following the steps described herein, however, with respect to FIG. 1D, the formed interconnect lines will be electrically isolated from each other where desired.
FIG. 1E illustrates another step in the formation of the interconnect. An anti-diffusion layer 26 is added over the interconnect line 24. The anti-diffusion layer 26 completely encapsulates the copper lines 24 and prevents the diffusion of copper atoms to the underlying and surrounding structures. Some typical diffusion barrier 14 materials include pure or alloyed cobalt (Co), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium tungsten (TiW) or silicon nitride (Si3N4). Other suitable materials may also be used.